SHA-RV: A RISC-V Accelerator for SHA-224/256 with Cycle Reduced ISA Extensions for Blockchain Applications

Dat Tuan Pham, Tuan Van Luu, Diem Thi Tran, Nam Hoang Dao, Duong Vu Trung Le, Tinh Van Nguyen, Thi Mai Pham, Nghia Xuan Pham

Abstract


The Secure Hash Algorithm SHA-256 and SHA-224 are widely used for software integrity, digital signatures, and blockchain across embedded and edge platforms. Prior RISC-V accelerators still struggle to achieve low cycle counts and high system throughput on long message streams. This paper proposes a hardware-efficient RISC-V accelerator with low-latency SHA instruction extensions, named SHA-RV, to reduce cycles and improve end-to-end performance. SHA-RV integrates three optimizations: a high-bandwidth BufferSet for continuous data supply, a four-stage pipelined SHA core, a system-level double-buffering pipeline, and an FSM-orchestrated BufferSet mapping. Implemented on a Xilinx ZCU102 system on a chip, SHA-RV operates at up to 300 MHz and uses 3,146 flip-flops, 5,175 lookup tables, and 15 block RAMs. On 64-byte blocks, SHA-RV completes a block in 257 cycles, improving over related RISC-V designs by between 9.7 and 134.9 times, while reducing logic resources versus the ISOCC 2024 design by 89.4 percent in flip-flops and 85.2 percent in lookup tables. At the system level, SHA-RV achieves a throughput of 599 megabits per second and an energy efficiency of 798.7 megabits per second per watt under a real-time dynamic power assumption of 0.75 watts, outperforming representative CPUs by between 61 and 454 times in energy efficiency. These results show lower latency and superior hardware efficiency relative to prior work.

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DOI: http://dx.doi.org/10.21553/rev-jec.423

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